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Intel`s Newest Itanium
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    Table of Contents:
  • Intel`s Newest Itanium
  • Increasing the Itanium FSB
  • Increasing the Itanium Cache
  • Grained Multithreading and Itanium's Future

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    Intel`s Newest Itanium

    (Page 1 of 4 )

    In the past I've written quite a bit on where Itanium came from, what it looks like inside, and gave a brief glimpse into where it is going. Today on DevHardware, I'm going to be getting deeper into just what was announced on Monday, as well as what we should be seeing from this project for the rest of the calendar year. This involves a technical look at the recent update to the Itanium2 lineup, as well as more details on what the codename Montecito means to the future of Intels "big iron" plans.

    What Intel announced was the release of a slightly modified version of the current "Madison" Itanium2 core. This new model varies from the previous one of the same name mostly in terms of how fast it communicates with the outside world; which also necessitates a new chipset (not that any servers or mainframes were going to be plugging these into older systems anyway). Intel is not providing that part of the system; their policy with regards to Itanium lately has been to only design the processors and the bus, leaving the rest up to integrators such as Serverworks and Hitachi.

    The current specs otherwise don't change much. The Madison core retains its options of 4, 6 or 9 MB of L3 cache, as well as clock speeds from 1.2 - 1.6GHz. The higher cache models are only found in the top clock speed grades (1.5GHz 6MB, 1.6GHz 9MB), the rest come equipped with the standard 4MB. On top of those are the two new models, both clocked at 1.66GHz and come with either 6 or 9MB of L3 cache. The reason for the odd number is the addition we mentioned above, a higher grade Front Side Bus (FSB) clocked at 667MHz.

    Internal CPU clock speed is generated by two factors: a multiplier value and the base speed of the FSB. In this case, the Itanium uses what is called a "quad pumped bus" in Intel literature. The basics of it are that for each clock cycle four operations are performed. I'm sure most of you are aware of DDR memory, which functions on a similar concept of two operations per cycle. This takes it one step further by having operations timed not just on the peaks and valleys of the swing of the voltage signal that represents the clock, but also at the halfway points of each swing as well. This allows for the use of a slower global clock while achieving much higher timing speeds.

    So what does this all mean? A 667MHz FSB in Intelspeak is actually running at 166MHz, leaving the 1.66GHz model with a 10x multiplier. Quite likely this is the last speed bump that Madison will receive before being replaced by Montecito (explained below), but future enterprise oriented processors (both Xeon and Itanium) will also make use of this same bus speed, width, and protocols.

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