Core Concepts - Merom
(Page 3 of 4 )
Merom, although launched post Woodcrest/Conroe, seems to have been the mold for the architecture from which Woodcrest and Conroe were cast. Intel wanted to build upon the successes of the Core Duo mobile chips, recently unveiled in the new Macs, extending the energy efficiency and performance features to desktop and server platforms and building on these with other innovations. The slightly slower bus speeds of 667 to 800 MHz and clock speeds of 1.83 to 2.33 GHz are offset by the power consumption of 45W and, as with the others, a shared two to four MB level 2 cache. I briefly mentioned some of the benefits of lower power consumption, but I just want to add that lower power consumption is especially important in mobile processors because lower usage equals a longer battery life. It also means less noise.
As I mentioned, Merom was the blueprint for Intel's new microarchitecture Core. It was even the code name for the new architecture way back when it was first conceived, and the Core architecture draws heavily on the successes of the Core Duo chip. Some of the innovations brought to the new architecture from the recent Core Duo chips include the dynamic shared cache, optimized power efficiency and multi-core on a single die.
The intelligently shared cache brings many benefits in power optimization and processor efficiency. Both cores have full access to all of the L2 cache, so when data has to be stored by the processor, it can store it where both cores can reach. This optimizes cache resources and reduces traffic on the front side bus. Also, when necessary, such as when one core is idle, one core can take control over the entire cache. The cache is dynamically allocated to each core depending on its needs, which increases performance while maintaining power efficiency. Cache ways can also be flushed to the system memory during periods of inactivity to save even more power.
The power efficiency of the processor is brought about in a variety of ways, including the ability to put each core independently into one of several low power states such as halt, stop clock and deep sleep. The deep sleep mode has been enhanced by Intel to reach lower voltage levels; this is done in conjunction with the smart cache flushing described above, and the state transitions occur very rapidly.
Next: Other Improvements >>
More Computer Processors Articles
More By Dan Wellman
| Recommended by Dev Hardware |
|---|
|
