Itanium Introduction - New Paradigms
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At the time, Intel only had the Xeon processor, which only could accommodate a handful of processors being tied together. In addition, the x86 instruction set Intel used was not optimized for the type of data sets these applications used. HP's PA-RISC (Reduced Instruction Set Computer) was going in the right direction, but really didn't have a lot of life left in it for future scaling. IA-64 (as it's known internally) was a complete break from anything done by Intel before, and expanded upon the VLIW (Very Long Instruction Word) work done by the late Bob Rau, taking some principles from RISC type architecture, and applying it to modern research in instruction set design. x86 (IA-32 to Intel) is ancient by comparison to every one of those, and is additionally based on a CISC (Complex Instruction Set Computer) design.
Author's Note: For a comparison of RISC and CISC, check out my article on x86-64 for Plug In Magazine, published April 2004.
Rau decided that instead of using clock speed to further performance, future processors would make use of parallelism. Unlike many desktop programs, databases and complex problem solving is usually able to be spread across multiple processors and within those processors. To accomplish this effectively however, both hardware and software design principles had to be changed.
First of all, much of the focus turned to the compiler. Instead of the CPU dynamically determining the best order to execute code, as well as figuring out what can all be done at the same time, this was henceforth to be determined at the time of the code’s compilation. This is the opposite of what is done on the x86. That’s because compilers, at the time that the x86 was first developed, couldn't generate fast code to the level of humans. With compiler design having come a long way, things now look very different. Intel has put a lot of R&D money into this because the company knew that in order for Itanium to be adopted, there had to be a base of software that it could run. Itanium is capable of running normal x86 code, but it’s painfully slowly.
From the hardware perspective, Itanium was created to max out the "reticule size" of a die. When you build a processor, it's done on a circular silicon wafer that contains many individual chips. The reticule size is how big each one of those individual chips is. The chip itself is huge (and I'll get into the layout of it in the next article), but for now, lets just say that while there are tons of execution units and a ton of register storage area, whatever room left over is taken up by cache.
Most designs try to aim for a 100mm square die size. Itanium2 is far, far beyond that, taking up an absolutely massive 418mm square, and eating 221 million transistors on a .18 micron process. Unsurprisingly, that also brings with it massive power consumption.
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