Pentium 4 overclocking tools?

Trying to overclock P4 1.7Ghz but cannot find any program that will allow it. My bios dosen't support overclocking and I am trying to suck all of whats left out of this machine (Dell). Clockgen wouldn't work with my system (Bios A01, Chipset i850, RDRAM 256mb at 400mhz, and FSB 400mhz. Anyone know any programs that I could use to overclock The old beast?

Can you open it up? Does it voids your warranty? Or do you care?

If you can open it up, look inside and get the numbers of the PLL chip.

Google for "PLL overclocking", or like you also said, ClockGEN is a great utility that allows overclocking via PLL. You said it does not autodetects your motherboard, it's ok. You can still overclock with that utility if you find out yourself the PLL IC that is used on your motherboard. Another utility that's like Clockgen is CPUFSB. Google, download, research, learn.

Notes: PLL stands for Phase-Locked Loop; IC stands for Integrated Circuitry

Check out the pictures below for a couple of PLL ICs:





List of a couple widely known and reputated PLL IC manufacturers: ICS, cMedia, RealTEK, Winbond, IMI, Cypress, etc.

Also, you can find out a lot more of and from PLLs. Learn how do they work.

Good luck!

Thanks, can you tell me anything about ram timings or changing them for the better?

http://www.cpufsb.de/FSB.HTM

You'll have to find out which PLL it uses yourself, we can't help you on that.

There's also a good chance you won't be able to overclock via software because the PLL is not connected to the SMBUS, so software cannot write to it... But that's not absolutely certain.

Only thing after that would be pin mods to change the default FSB speed of the CPU and you'll probably need more voltage to do it properly because your CPU is a Willamette, and they weren't the best overclockers... In fast, 133MHz FSB may be asking a little too much (after some research, it looks like it is too much...)

EDIT: Bah, looks like I took too long researching Willamette overclocks! I blame my crappy internets.

Only thing I can suggest is WPCREDIT and then WPCRSET when you've fully tested your settings. I have no personal experience with RDRAM so I can't tell you what's good and what's bad to tweak with it... All I can do is tell you you should either find an i850 PCR file for your chipset (which I can't find) or download the datasheet from Intel and do it that way.

If you can get your head around it, WPCREDIT is a great program, but if you can't... You're a bit stuffed.

Well thanks for the help, I hope it will workout but I don't know.

Ok I downloaded cpufbs and it says frequency to set, not used, and it says get PLL output, but then says getting PLL data can damage my hardware what should i do? Also the settings it has to change the fsb are already lower then what it is know. And one final thing how do I know what my pci speed is? All the options seem to be much less than mine They are at like 50 to 100 mhz mine is at 400mhz. Is it getting multiplied?

Yes it gets multiplied. Your actual speed is 100MHz, it somehow gets turned into 400MHz inside the Northbridge (I don't think anyone knows how). Anyway, how it happens isn't important... Also, when overclocking, there's always a chance of damaging your hardware. If you can't afford to lose it don't overclock - simple. However, if you're sure you've chosen the correct PLL, chances are minimal that the machine will even lock up, let alone get damaged.

Your PCI speed will be one third of the FSB speed you choose. Unless the i850 has PCI/AGP locks, I don't know, I've never even seen such a machine let alone played with one.

If your PLL does not go above 100MHz, then you're a bit stuffed anyway, to be honest. Unless you want to break out the soldering iron, but that's a whole different story...

Do you let me/want me to drift off-topic? I bet you do...

john-luke, you may skip this post, or grab your coffee and/or juice/beer and enjoy...

(The 100MHz still remains 100MHz but it's going to work as effectively as 400MHz via pumping.)

Double-pumping & Quad-pumping --how do they work?

I won't go into the basics and want to keep my post strictly on the target, detailed, specific and essential (towards everybody, not just Snod). I'm assuming prior knowledge regarding quad-pumping and double-pumping, the basics. Why and how it happens?

First of all, what is pumping? It means how many times data is transmitted through one clock cycle. Common sense, the more the better.

Years ago, SDRAMs (=synchronous dynamic random access memory) could transfer data only once per clock cycle. Later on, DDR SDRAMs (=double data rate synchronous dynamic) were invented, they are capable to transfer data twice per clock cycle. Thus their performance is literally doubled (theoretically). How this was achieved? At first with first-era SDRAMs the data was transmitted on the peak of the cycle. Second generation DDRAMs' architecture was capable to transmit data on both the crest (peak/high level) and the trough (low level) of a cycle. This was on an architectural level allowed and chips/sticks were designed to handle this vast majority of data.

Check out the following picture of a simple graph, there's pointed both the crest and trough of a wave.



To sum this up, basically with double-pumping bus speed the processor could transmit data (send/receive) twice per clock cycle. Just as with DDR-SDRAMs sticks we've already discussed about.

Now if the information above makes sense then it's clear that Quad Pumping (QDR) basically means that a processor could transmit data (send/receive) four-times per clock cycle. Yet again, literally doubling the performance (again, theoretically)! Coupling P4 processor capable of quad-pumping with SDRAMs caused a huge bottleneck-- completely understandable; thus the lack of data speed. RAMBUS memories were designed to come to the rescue. These memories, even though, they were (only) double-pumped, they've got high enough frequency speeds not to bottleneck the CPU. Example of RAMBUS memory: DDR 400MHz (double pumped) - 800MHz. These memories being capable to send/receive amount of data 2 times per cycle were a big improvement and reduced the bottleneck a lot. Ultimately the technology advanced and Dual-Channel DDR memories were out, capable of enough performance to reduce bottleneck too and were/are way cheaper than RAMBUS memories. That's why the market instantaneously got flooded with Dual-Channel DDR sticks, kits.

As far as I know (correct me if I'm wrong) in case of quad-pumping (QDR) and DDR SDRAMs, the difference between '4 accesses per clock' and '2 transmits per clock,' the bus speed makes up the difference; those 2. I don't know how this is done but in case of synchronous accessing it should make up.

So to sum this part up again, basically quad-pumping works by the following procedure: it uses the beginning of the rising clock (middle-left); the end of the rising clock (crest/peak); the beginning of the falling clock (middle-right); and the end of the falling clock (trough/low-part); to transmit the amount of data 4 times per cycle. Those additional informations as 'left' and 'right' are just stated to help you imagine them on the graph-wave I've posted below. In real-world the process is similar, though.

Here's the wave...



Additional notes: Simple example of the well-known DDR400 (PC3200). How it works? 200MHz x 2 transfers/s x 8 bytes/transfer = 3200MB/s, thus the reason why it's called PC3200. This is the same with PC2700, PC2100. The above equation is the base. Of course, two well-matched sticks (dual-channeling that I won't get into now) are capable to perform at double numbers, for example 2xDDR400 sticks could provide with 2x3200MB/s, resulting in a total of 6400MB/s (theoretically).

Memory latencies do play a big role in overall memory and system performance: i.e. [CAS], [tRCD], [tRCP], [tRAS], [CMD Rate], [Cycle Time], et cetera (correct use of etc). You all know that...

I will perhaps edit my post later-on if I can come up with additions or something. Either way, few recommendations now (for Snod ). Read EVERYTHING you can find that's written by Jon "Hannibal" Stokes (thanks Arch, again). No matter how old the article is and/or seems like-- read it. Also 'A Quantitative Approach' by John L. Hennessy, David A. Patterson (thanks Tejas) is something that I can recommend whole-heartedly; that textbook is purely godlike. I'm struggling myself with it since days and will for months/years.

Appendix- links:
Understanding Bandwidth and Latency by Jon "Hannibal" Stokes
HyperTransport Moves Closer by Jon "Hannibal" Stokes
Dual-channel DDR comes to the P4 by Jon "Hannibal" Stokes

Wow Thanks for the info. Ill See What I can do.

Not to bump or anything, but I recently looked at CPUFSB and the list of PLL bridges and manufacturers that was supported in that program. Then I looked at CPUCooL and it looked like it had a more extended list of supported PLL bridges. From that point, I was able to find the one I had and overclock a single-core Celeron D on an eMachines W3502. The proof: