Page 2 - Whats better - Larger Cache or Faster Core?

I wanted to follow up with info that my 300watt no name PSU started stumbling with the higher wattage processor, new 80watts, so instead of jeopardizing the mobo and everything else in the case, I ordered a new Coolermaster 500watt PSU and didnt turn on the computer until this new PSU arrived.

I really dont know what to say, but these old games kick ass now. I left the 6600GT at stock speeds, and in both my games, fps has gone from an average of 15/20fps to about 35/40fps with max fps at 55 and 84fps, running 2xAA and 4xAF

The larger cache was definately the way to go and I thank all of those who gave input on this decision. Now this old system will get me by until I get some money saved up for another upgrade or totally new system!

Jammerx99

P.S. I understand the arguement about wasting money on an outdated processor, but with limited funds, I didn't have enough to get a more recent CPU, which would have required a different mobo, memory, heatsink, and GPU - so I went with what I thought would be best for what I have!!

honestly though, either way, your new setup will be outdated and will meet its match right out of the box.

Just a note to this topic

jammerx99 choosed from two much different CPUs :
Athlon 2700+ was last model of Thoroughbred core on 266 MHz
Athlon 2800+ was in the middle model of Barton core on FSB 333 MHz

Agree with all here that 2800+ have better performance not only because of bigger cache L2 but with higher FSB and OC potential.

AND most important 2700+ as last model of FSB 266 Mhz is much harder to find and much more expensive in same time.

Glad to hear you that is all OK with your RAM and motherboard with new CPU.

Just a note, even though it is an old thread...

IIRC, Athlon Xps don't have SEE2, do they? That becomes crippling on a lot of modern software.

i dont think so, no, they shouldnt.

SSE2 isnt used everywhere IMO, but SSE, yes, and athlon xps do have SSE. SSE3 is available in A64s Venice and more recent, but SSE3 isnt much of an acceleration...

As for pre AXP, thunderbirds didnt have SSE. i doubt any of the pre AXP has SSE, whcih is extremely cripling.

Hopefully my post will shed a bit of light on the previously mentioned information and insight. Its purpose is clarification.

I think my post contains the most accurate details and specifications about those two Athlon XP processor since their specs aren't recalled from memory. I've attached references and further reading links to articles and specific sites that I've used thorough my post to clarify and illustrate. In-depth information is included, hope you will enjoy.

Name: Athlon XP 2700+
Frequency: 2167 MHz
L2 Cache Size: 256 KB
FSB: 333 MHz
Multiplier: 13x
Core Voltage: 1.65 V
Maximum vCore: 2V
Max Core Amperage: 41.1A
Typical Power Dissipation: 62W
Max Power Dissipation: 68.3 W (B model)
Released on: October 1, 2002
Part Number: AXDA2700DKV3D

Athlon XP “Thoroughbred B” – model 8 - built on 130nm.

Thoroughbred ‘B’ has an extra layer of cooper interconnects to reduce interference compared to the ‘A’.

Supports the following technologies: MMX, SSE, Enhanced 3DNow! (aka 3DNow!+ or Extended 3DNow!)

CPU-ID: 6-8-1 (B model)


Name: Athlon XP 2800+
Frequency: 2083 MHz
L2 Cache Size: 512 KB
FSB: 333 MHz
Multiplier: 12.5x
Core Voltage: 1.65 V
Maximum vCore: 2V
Max Core Amperage: 41.1A
Typical Power Dissipation: 53.7W
Max Power Dissipation: 68.3 W
Released on: February 10, 2003
Part Number: AXDA2800DKV4D

Athlon XP “Barton” – model 10 - built on 130nm.

Supports the following technologies: MMX, SSE, Enhanced 3DNow! (aka 3DNow!+ or Extended 3DNow!)

CPU-ID: 6-10-0


Both of the aforementioned processors are running “double-pumped” meaning that their FSB runs at twice of the square wave generator that controls obviously the system clock (i.e., 333MHz FSB runs the wave generator on 166MHz – meaning that the data is transferred at the peaks of the imaginable graph; at the crest and the trough). The attached diagram/illustration below should illustrate visually where the previously explained procedure happens.



--

Pre-Athlon XP processors didn’t support any sort of SSE. The Athlon ‘Argon,’ (250nm) ‘Pluto/Orion’ and ‘Thunderbird’ (180nm) cores sported only MMX and 3DNow! All three of these have had almost similar L1 cache architecture and that was separated one for data and one for instructions, both of them being 64KB each. Thunderbird was the best of that era because its L2 cache gained numerous technology breakdowns, out of which was incorporating on-die 256KB of amount and running it on full speed (that was an achievement compared to the previous two processors —Argon and Pluto/Orion— that were having 512KB of L2 cache but off-die as external chips on the CPU module and were running with theoretically up to 50% of CPU speeds and practically varying from 30%-45%. Those two were double-pumped too with front side bus of 200MHz (2x100MHz), whilst the Thunderbird was running on 200-266MHz (2x100-133MHz), the A-B models on 200 and the C on 266.

Athlon XP’s most crucial specification was the integration of SSE (Streaming SIMD Extensions where SIMD stands for Single Instruction - Multiple Data).

SSE’s (Feb, 1999) history is quite long and complex, it was designed by Intel and was planned to be released on PIII’s codenamed ‘Katmai.’ SSE came to the rescue to save the ‘computing’ from the disappointments that were gained from MMX and a reply to AMD’s ‘3DNow!’ that debuted earlier. Disappointments were because MMX technology was capable to work only on integers (major con), plus the CPU could not work simultaneously on both floating-point operations and SIMD data (even more drastic). This was because they both have shared one single register space (thus you can’t mix in the data inside a register simultaneously). Therefore it was a hit on superscalar execution —performance— because it slowed down overall CPU output (too many cycles were used only on SIMD instructions/data whilst the rest of the processor was, perhaps, idling). Just a little side note: MMX’s vectors are only 64 bits wide (subdivided into 8, 4 and 2 elements) and in total MMX added 57 instructions to the x86 ISA.

Drifting back in a past a little bit… AMD’s ‘3DNow!’ debuted in 1998. Its purpose was to enhance the performance capabilities of the MMX (by fixing some of the previously mentioned issues). Basically it was an extension set to the x86 ISA and it improved vector processing capabilities—running mathematical operations on multiple data elements simultaneously. It contained a total of 21 new instructions. Later on the 3DNow!+ (extended) was released with 19 new instructions. Although after the success of Intel’s SSE, AMD combined Intel’s SSE (as a whole, without modifications AFAIK) to their very own 3DNow!+ and that how 3DNow! Professional was made.

SSE added 8 new XMM registers (128-bit) that helped big time. SSE was able to mix SIMD and scalar floating-point operations without performance hit. Even though, there was a negative side of the SSE too and that was limiting the effectiveness of pipelining; the processor will not issue instructions related to SSE and to Floating Point Unit (FPU) at the same-clock cycle. Anyway because MMX didn’t ‘disappeared’ it was still a great benefit, basically the processor remained with two new technologies, one being the older one MMX and the new SSE, therefore in certain cases it was possible to run in parallel simultaneously both MMX and SSE operations thus an almost-double performance improvement. On an architectural level the aforementioned action was possible because MMX’s 8 registers remained there and SSE’s 8 (128-bit) registers were additionally added, all of these totaling and leaving enough space for the data to be stored individually and respectively.

SSE’s vector integer operations were limited to the 64 bit (using the old MMX registers) and the vector floating-point operations on single-precision (only). This was fixed with by SSE2. SSE2 made possible to store 128-bit integer vectors into the registers, plus it enhanced the single-precision to double-precision (64-bit). SSE2 adds a total of 144 new instructions. Basically SSE2 finally made it possible all that Intel already wanted with its previous successor the SSE(1).

SSE3 released in 2004 added 13 instructions to the SSE2. SSE3 is capable to work ‘horizontally’ in a register whilst previous SSE’s (2 and 1) could only work ‘vertically.’ Also, several additions and performance enhancement were added (i.e., enhancing the conversion of floating point values to integers and new additions to prevent the appearance of pipeline stalls).

SSSE3 (Supplemental SSE3) and it’s often referred as SSE4. Intel considered SSSE3 as a revision rather than a new technology to increment its name to 4. It adds 16 new instructions to the SSE3; each can act on MMX (64-bit) and XMM (128-bit), therefore a total of 32 new instructions. It is sported by Xeon 5100 and Core 2 Series.

SSE4 should be released somewhere around 2008 and the processor ‘Penryn’ codenamed might contain most of the SSE4 instructions (if not all). Apparently it will add 50 new instructions to the already existing SSSE3. We will see. Ambiguous news and predictions are all-around but we can’t know for sure until the official release and data.

References and further reading:
http://www.c627627.com/AMD/AthlonXP/
http://www.amd.com/us-en/Processors...182_739,00.html
http://www.intel.com/technology/itj/archive/1999.htm [Q2, 1999,Vol 3--Issue 2]
http://fab51.com/cpu/guide/opn-xp-e.html
Wikipedia
ArsTechnica
http://www.dailytech.com/article.aspx?newsid=4358
http://www.intel.com/technology/arc...spx?newsid=4358 (ref. to SSE4)
Jon Stokes: “Inside the Machine” (pages 174-175, chapter 8; first edition) -- also don't forget to check out my review of the book.

PS: I didn't proofread my post.

Sounds about right. Actually perfect. I know now that MMX and SSE are often required. Many softwares are optimized for SSE2, and slowly, some SSE3, but aren't yet dependant.

The only software I know that requires SSE3 is Intel Mac software. Rosetta, the software that translates PowerPC code to Intel code uses SSE3, as well as parts of the GUI. (The Darwin kernel, however, is only dependant on SSE2). Macs all ship with X-VT technology as well (The 6xxx series Core 2 Duos, and original Core Duos), so all virtualization software for Macs runs on VT Required. However, the original Core Duos that shipped with Macs were not EM64T enabled, so they may be soon left in the dust, when they go full 64-bit. (Could they cut off early Intels BEFORE G5 PowerPC, (Probably not, they'd probably cut PowerPC alltogether.))

My Core 2 Duo is an E4300, so I have MMX/SSE/SSE2/SSE3/SSSE

Nice post, BTW, rep you I shall, once I get more rep for you again, already did in the thread entitled "OpenGL GUI"

man i absolutely despised half speed l2 cache on the katmais... made it so beepingly slow compared to my full speeed cache processors, even if it was 512k l2 versus 256k l2.

perhaps you should have mentioned the exclusive and inclusice l2 cache architechture and and intel use. little detail though and not as significant.

also, another detail, the original thread started was comparing the 266 mhz fsb thorouhbreds to the 333mhz fsb bartons...

Show me an Athlon XP 2700+ running on 2.170GHz with 256KB L2 cache that is Thoroughbred and runs on 266MHz FSB.

... you won't find one.

Other than that I agree with you, Dragon_fly.

@steve_twp: I'm glad and appreciate your comments. Reputation != taking time to post and say "nice post."