Quad Core AMD's

Wondeer how much these puppies are gonna cost .........Quad Core AMD!!!!!!!!!


http://enterpriseevent.amd.com/mome...id=geek&lang=en

Intel's going to release their Quad-cores by the end of this year..when are these coming out? {using a system with no sound..}

hey just a quickie,are the quad intels still can have the quad pumped tech. in each processor or or they changing that?

Quad-Pumping refers to the frontside bus. So yes, it should still be there with the quad-cores, because when you double the number of cores you're doubling the amount of data that needs to be sent along the front side bus. Intel isn't switching to a completely new interconnect system anytime soon, so they'd better hold on the the quad-pumped FSB and if possible crank the clockrate up a bit too.

Actually the Core architecture hardly requires much bandwidth at all. Very little benefit between 166FSB and 400FSB. Shouldn't be too starved with quad core.

....oh and just for the record...and for the gloat...I handled a Kentsfield (quad core) last week...

I thought I'd read it was pretty bandwidth hungry, somewhere... meh. I'll have to go looking some time.

so there will be a total of 16 PROCESSing cores
running!?How many L cashes does that work out to?

Ya ya ya, you handle all of intels cpu's early on. Pretty sweet though.

I think you are confused.

Quad-pumping only refers to the front side bus. The front side bus (FSB) is the interconnect - the path for data on the motherboard - between the CPU and the chipset. Quad-pumping is how Intel gets to the high speeds of the FSB. It is kind of like DDR. With DDR (double data rate) you can send a signal on the up and down of an electrical pulse on a wire. So, take DDR RAM for example - it really only runs half the speed it says. DDR 400 is really only running 200MHz, but it sends data twice per MHz so it is like having 400 MHz RAM. Same idea but somehow Intel double DDR. They can keep a low "real" clock on the FSB, and then send data multiple times per hertz.

This has nothing to do with the CPU itself. The quad-core CPUs will only have 4 cores.



How many L2s will it have? I would have to look, it depends on how they decide to implement it.

2x4MB L2. One per pair of Cores. It's basically two Conroes slapped on one die.

oooh, aaah. Wow now that would be nice, would kick butt at multi-tasking.

It'll be interesting to see what happens with this and AMD's quad-core. Overall from what little I've read I like AMD's implementation better, it'll be more inter-connected and use a shared L3 (or maybe it was L2, but I doubt it...), much like the first time around when Intel basically slapped two Pentium 4's together and called it good. The difference is, Conroe isn't dying to begin with as the P4's were, and if software is set up properly maybe communication across two pairs of cores wouldn't be as much an issue if you keep threads that need each other on the same pair of cores...

thanks for un confusing me.I now have a better understanding.Help me understand this...the L1 cashe stores memory in anticipation of the processor asking for it.if the L1 does not have the right info it then goes to the L2 cashe which has stored memory that it also anticipates that the processor will ask for. If it misses it is then moved onto the main memory to retrieve what is being asked for.Is that how it works and how does the controller fit into this?(I got into a conversation that went through my legs & over my head at the same time) Does any of this make sense to you or am

Intel have each pair of cores with shared L2. They wanted to really rush the quad core, so they just slapped them together and moved it to 65nm.

Basically, yes. It gets more confusing if you want to fo more in-depth. For example, a 128KB-L1 is sometimes split into two 64KB L1 caches to store two different types of data. And depending on the CPU, other games are going on too; on the Pentium 4 for example, code was broken down into the individual operations the CPU could process outside of the processor pipeline to help the long pipe perform better. I forget exactly how all that was stored, but it could mean for example L1 could have individual ops broken up, whereas in L2 it still might be 'compressed' as high-level instructions. Meh. We're reaching the limit of my knowledge in this area.




I assume you mean the memory controller?

The memory controller is used to access system RAM, it does not deal with cache - the processor deals with those directly.

I can't say I know much about how exactly a memory controller works, but basically it's a go-between betwixt the CPU and the RAM. I'd guess it organizes requests and prioritizes them. Thinking about how little logic is on a stick of RAM, the controller is probably in control of accessing, reading, and writing everything to the correct memory address, and to do that, it'd need to figure out where to put it physically on the sticks of RAM.

Hope that helps, I'm a little iffy on the last one...