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MEMORY

Effects of Memory Latency
By: jkabaseball
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    2004-11-30

    Table of Contents:
  • Effects of Memory Latency
  • Testing Setup
  • Testing=SuperPi, Sandra
  • LAME, WinRAR
  • 3DMARK01 SE, DOOM 3
  • Conclusion

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    Effects of Memory Latency


    (Page 1 of 6 )

    If you’re in the market for some new memory, you will see modules ranging in price. The cheaper memory might not be as attractive, maybe no heatsinks, while the more expensive memory can come with anything from colored heatsinks to L.E.D.’s. Both are rated at the same speed, so are you paying all that extra money for the colored heatsink and flashing L.E.D.’s? Most likely not, each contains different chips, with different CAS latency. We will explore what exactly memory latency is, and how it affects your system’s performance.

    What is Memory Latency?

    When we see what a RAM’s CAS latency is, it is 4 numbers, such as 2-2-2-5, which correspond with CAS – tRCD – tRP – tRAS. You should be able to change the CAS Latency in your BIOS. In most BIOSes, it can be found under the “advanced chipset” menu, though it can be found in different areas in different BIOSes.

    CAS stands for Column Address Strobe. This is the number of memory cycles that pass between the time a column is requested from the active page and the time the data is ready to send across the bus. This number is usually 2, 2.5, and 3, on DDR memory. This is actually the last part to come into effect.

    RAS to CAS Delay is referred to as tRCD. This is the delay in memory cycles between the time a row is activated and when data within the row can be requested. This only happens when data is not on the active row.

    tRP is the time for RAS Precharge. This is the time in memory cycles that is required to clear out the active row out of the cache, before a new row can be requested. In other words, it’s the time it takes for the memory to stop accessing one row and start accessing another. Once again this only takes place it the data is not in the active row.

    tRAS refers to the minimum time that a row must remain active before a new row can be activated in each memory bank. A new row can not be opened until the minimum amount of time has passed. If there is more than one bank on memory, this will help the performance of the tRAS. If there is only one active bank, then the need to change rows is guaranteed, and if there is more than one bank with memory, then there is only half the chance that there will be a need to change rows. In turn, the tRAS will only come into effect half the time. The tRP and tRAS together are often referred to as the Row Cycle time, because they happen together.

    Let's compare this to a library. Let's say you want a book about Florida. Let's say the librarly is putting books away, and you ask for the book on Florida. The librarian would have to get off the ladder, move the ladder to the travel section, and then get back up on the ladder. This would compare with the tRP. The tRCD would be the time the librarian is at the right shelf and right row of the bookcase. The tRAS would be the time when the librarian finds the books about Florida, and when he finds the specific book you want. The CAS latency in this case would be the time from when he takes the book off the shelf, and the time it takes him to walk back to you. If he walks fast, it might be 2; if he walks slower, the number would be larger. 

    Let's say the library is putting books on Florida back; then the time required would be a lot less. All of the moving of the ladder would not be needed. This could happen in the memory if the data needed is on the active row. I hope this helps you understand how memory latency works. 

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