PCIe Primer - Basics: PCI
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One might ask “If AGP is better than PCI, and PCIe is based on PCI, then how could PCIe be better than AGP?” This is a completely valid question. And the answer is simple. PCIe is not just a one-off or "rigged" PCI, it’s a whole new approach using similar building blocks.
For starters, PCI used what is called a "shared bus topology." This means that all devices plugged into PCI slots share the bus, and the bandwidth. This has been the major problem with PCI all along. When you think of a high-throughput device, such as a Gigabit network controller, and then consider that the max theoretical speed of the whole PCI bus is 133 Mbps, you can see how a 1GBps device is already being throttled down. Even a 100mbps network card would have a hard time working at its full capacity, if any other devices are being used on the PCI bus. Installing a PCI sound card would then make the two devices compete for, and share, the total 133mbps allowed by the PCI bus.
Now, each of the PCI devices in the above diagram contain some control logic, to help manage the communication on the bus. In other words, these devices get to duke it out, to find out who gets to run the bus (the bus master). This one device gets to communicate to the CPU and RAM, while all the other devices have to wait their turn. This isn’t a very intelligent way of doing things, is it?
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