x86-64: The Golden Handcuffs - CISC vs RISC
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Right now, the only mass-produced CISC processors are those that dominate the desktop market, the x86 processors from AMD and Intel. Since the 80s, many newer RISC processors have tried unsuccessfully to knock CISC off the map entirely, and been completely unsuccessful in doing so in the mainstream desktop market. While the lines are starting to get blurred between the types, I’ll do my best to explain the difference between them.
CISC came along first, and was meant to take the complexity away from the compilers (which weren’t very good back in the 60s-70s) and put it in the hardware. This reduced the lines of code, as actions like multiplication or addition, which needed operands from memory, took only one instruction. Additionally, CISC machines typically have a small number of specific purpose registers. Since the number of variables in code is usually higher than 3 or 4 at one time, this induced a lot of what is called register spilling. With a smaller amount of area to hold these variables at one time, some must be moved in and out of memory (which is a permanent place for holding data).
Newer CISC designs make up for register spilling by having more “hidden” registers, into which values can be moved temporarily by the hardware. However, you can’t use them from the programmer’s model. CISC architecture is typically known to be a “register- memory” or “accumulator” type. This means that in most cases, operands are capable of being specified from memory, as well as the registers. This adds to the complexity of the instructions, which first have to move the data from memory to the register, then execute, and finally update whatever values were worked on. Complex instructions mean complex hardware. Even though transistor size allows for large numbers of instructions, the metal wires which interconnect units--as well as move data around, relay the control signals, and complete other communications necessary to run the CPU--are starting to get overloaded.
RISC has been developed for over 20 years now. Unlike CISC, it moves the complexity to the compiler. Today, compilers are capable of making better low level code than humans, tailoring specifically for more complex architectures, and easily switching between different designs. This allows the processor design to be much simpler.
These “load/store” architectures typically allow for operations to only be executed on registers, meaning that you have to explicitly bring in each piece of infor-mation to the register file. What might be one instruction on a CISC type implementation might take 4 on a RISC machine (load one operand, load the second, execute, and store back to memory), increasing code size. This might seem slower, but four instructions don’t necessarily mean slower performance than one instruction. Remember, all those same things have to be done in the CISC instruction, they just are just done by the hardware on its own. By removing this complexity, there is more die space left for other uses of transistors.
Typically, RISC style machines have many more “general purpose” registers (GPRs) available to the compiler. Older designs of MIPS (Stanford) and SPARC (Sun) for example, as well as PowerPC (IBM) and Alpha (DEC) had 32 GPRs. Newer ones have even more; x86-32 machines, such as your current Athlon XPs and Intel P4s, by comparison, have eight GPRs. Itanium (IA- 64) has a massive 128 GPRs available to the compiler. By having more GPRs, there is less of a need for load/store commands to slow (relatively) memory, especially in looped code.
As I said, the lines are blurring. x86 based processors have become more like RISC. With the introduction of 80386, eight of the specific use registers from 80286 became “general purpose,” in addition to being extended from 16 to 32 bits. Some RISC designs have had CISC type instructions added to their ISAs in order to fill specific needs in various multimedia applications.
There are still some key differences. Most specifically, x86 still has many different sizes for each type of instruction. There is no specific length, depending on the extensions needed to choose from operation size (8, 16, 32, and now 64 bits), regardless of whether its meant for the MMX, SSE, x87, or normal execution units, what type of instruction it is, and so on. In most RISC designs, the instructions are all one length, again taking away some complexity.
Next: x86-32, IA-64, And Now x86-64 >>
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