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Into the Itanium, Part 3
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    Table of Contents:
  • Into the Itanium, Part 3
  • Madison vs. McKinley
  • Through the Pipeline
  • Introducing Montecito

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    Into the Itanium, Part 3 - Through the Pipeline

    (Page 3 of 4 )

    The integer pipeline control circuitry is actually quite small. With a very short pipeline, and the fact that there aren't any reservation stations (for out of order execution) or the other registers related to that, cleans this area up significantly. This is one area where moving complexity to the compiler has benefited. Itanium doesn't have as complex of a structure for decoding instructions, and addressing is much simpler compared to x86. RISC (and EPIC because it's derived from that) instructions are small to begin with; they are roughly equivalent to the basic building blocks that make up a complex x86 instruction. That frees up space for other hardware. As well, the hardware does not have to seek out instruction level parallelism to ship off to the various execution units, as the instructions come prepackaged in "bundles" with parallelism sorted out at compile time.

    The same thing works for the floating point path. Instead of wasting your transistor budget on things that don't add performance, it's put towards extra units. There are both 2 82 bit and 2 32 bit units there, for single and double precision operations. After all, if you don't need the extra precision, why waste precious resources that could go to operations that do need it? This is one of the reasons why  the Itanium's floating point performance is so ridiculously high.

    There is also a multimedia unit for supporting MMX instructions. Why is that needed? Well, it's a part of the added on x86 support that Intel felt necessary to tack onto the Itanium. You can see the rather large IA-32 emulation unit. This is the part that takes in your typical x86 instructions, decodes them, then turns them into something that the IA-64 units can understand. Considering the performance is roughly similar to that of a Pentium at 200MHz, I'm not sure why they even bothered. For someone to spend multiple thousands of dollars on a single chip, they couldn't possibly do it and expect that level of performance. With it being that dismal, it's not worth adding in the compatibility, especially considering the prodigious performance of code that is compiled specifically for this architecture.

    So that's the current state of affairs. But what about the future?

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