Computer Processors

  Home arrow Computer Processors arrow Page 2 - Into the Itanium, Part 3
Watch our Tech Videos 
Dev Hardware Forums 
Computer Cases  
Computer Processors  
Computer Systems  
Digital Cameras  
Flat Panels  
Hardware Guides  
Hardware News  
Input Devices  
Mobile Devices  
Networking Hardware  
PC Cooling  
PC Speakers  
Power Supply Units  
Sound Cards  
Storage Devices  
Tech Interviews  
User Experiences  
Video Cards  
Weekly Newsletter
Developer Updates  
Free Website Content 
 RSS  Articles
 RSS  Forums
 RSS  All Feeds
Write For Us 
Contact Us 
Site Map 
Privacy Policy 
  >>> SIGN UP!  
  Lost Password? 

Into the Itanium, Part 3
  • Search For More Articles!
  • Disclaimer
  • Author Terms
  • Rating: 3 stars3 stars3 stars3 stars3 stars / 11

    Table of Contents:
  • Into the Itanium, Part 3
  • Madison vs. McKinley
  • Through the Pipeline
  • Introducing Montecito

  • Rate this Article: Poor Best 
      Del.ici.ous Digg
      Blink Simpy
      Google Spurl
      Y! MyWeb Furl
    Email Me Similar Content When Posted
    Add Developer Shed Article Feed To Your Site
    Email Article To Friend
    Print Version Of Article
    PDF Version Of Article


    Into the Itanium, Part 3 - Madison vs. McKinley

    (Page 2 of 4 )

    Into the Itanium

    The "Madison" Itanium2's, like their McKinley predecessor possess full speed L3 cache on board, unlike the original Merced core which had it on the card, but not directly a part of the die itself. Looking at the diagram of the chip, that cache takes up an awful large portion of the area count, and especially the transistor count. The cache is the area surrounding the core of the chip, all along the bottom and right side of the die.

    Into the Itanium

    This is a diagram of McKinley. You can see the obvious difference in cache size between the two. However, since this one is so nicely detailed already, I'm going to use it to map the architecture for you.

    Data comes in through the front side bus, from the outside world that exists thanks to RAM and permanent storage accessed by the chipset. The current Itanium2 bus is a 128 bit wide, 400MHz one. While this is certainly sufficient for one CPU, the design calls for up to four separate Itaniums to be hooked off of it. That is definitely a possible choke point for any multi-processor system based on this architecture. From there the logic can port it off to any address in the L3 or L2 cache. Looking at the diagram, you'll notice that the L3 is a "unified" cache,  same for the L2. This means that both data and instructions can reside here, as well as information relating to integer, floating point, or x86. The L1 cache contains either data or instructions; it's split separately according to the type of information that will be stored. In the L1, only information relating to integer operations is stored, floating point goes directly from the L2 to the 128 specific floating point registers.

    More Computer Processors Articles
    More By DMOS

    blog comments powered by Disqus


    - Intel Unveils Itanium 9500 Processors
    - Intel`s Ultra-Quick i5 and i7 Processors Ava...
    - Intel Nehalem
    - VIA Nano
    - Intel Atom
    - Intel Celeron 420
    - Intel Pentium E2140
    - Inside the Machine by Jon Stokes
    - Chip History from 1970 to Today
    - A Brief History of Chips
    - Intel Shows Off at Developer Forum
    - Core 2 Quadro Review
    - Core Concepts
    - AMD Takes on Intel with AM2 and HT
    - Intel Presler 955: Benchmarking the First 65...

    Developer Shed Affiliates


    © 2003-2019 by Developer Shed. All rights reserved. DS Cluster - Follow our Sitemap
    KEITHLEE2zdeconfigurator/configs/INFUSIONSOFT_OVERLAY.phpzdeconfigurator/configs/ OFFLOADING INFUSIONSOFTLOADING INFUSIONSOFT 1debug:overlay status: OFF
    overlay not displayed overlay cookie defined: TI_CAMPAIGN_1012_D OVERLAY COOKIE set:
    status off