Intel`s Newest Itanium - Increasing the Itanium FSB
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What is the point of increasing the front side bus speed, but barely bumping the overall clock as well as not changing the cache size or structure? In the case of the Itanium2, a lot. Since its introduction, which seems like forever ago, it has suffered from inadequate bandwidth coming in the front end. The boost to 533MHz FSB helped to quell that issue for single and dual CPU designs (the models without the massive 6 and 9MB caches), but has not been available for multiprocessor systems with larger numbers of sockets.
Due to how the processors are connected to one another, up to 4 have to share that one pipeline to the chipset (clocked in at a slower 400MHz to reliably handle the extra load of being attached to so many chips). This is certainly a problem even with the massive amounts of cache each CPU carries on board. The overhead for chips communicating slowly over the front side bus is that their cache fills with files, which are locked until they receive more data to continue processing, and this increases "dirty" data. This overhead is not insignificant, and currently it is quite the drawback even with the increased frequency.
Other multiprocessor designs tend to have a specific crossbar used only for networking CPUs to one another. Then the FSB can be used purely for getting data to and from the chipset, with administrative CPU-to-CPU work going over the crossbar.
In order to try to correct this design flaw without completely redesigning the structure, future dual core models (Montecito) will have a "dual FSB." This dual FSB is where the chips essentially double the throughput to quad socket blocks, where each pair of sockets receives its own 667MHz bus; this is opposed to sharing just the one bus amongst them, as in the current design.
From the outside this sounds like an outstanding improvement, until you recognize the wording I used. That is the "per socket" bandwidth, not per CPU. With the new design carrying two processors per socket (as well as two busses per 4 sockets), the only advantage will be from the boosted clock speed. The two sockets/four cores will be sharing 166MHz (667/4) if they were all demanding an equivalent load on the bus, as opposed to 100MHz (400/4). So while in a quad CPU arrangement this is an improvement, it's not a massive increase of per CPU I/O like it would seem when you consider the increased number of busses and additional clock speed.
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