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COMPUTER PROCESSORS

Cell Inside, the Future of Processor Architecture
By: Developer Shed
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  • Rating: 4 stars4 stars4 stars4 stars4 stars / 216
    2005-06-29

    Table of Contents:
  • Cell Inside, the Future of Processor Architecture
  • Cell Architecture
  • PowerPC Processing Element (PPE)
  • Synergistic Processing Element (SPE)
  • Element Interface Bus (EIB)
  • The Future of Cell and x86
  • It's the Software

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    Cell Inside, the Future of Processor Architecture - Element Interface Bus (EIB)


    (Page 5 of 7 )

    All this information running around inside the processor has to travel on the Element Interface Bus (EIB). The EIB is located in the middle of all the other pieces of the processor and consists of four 128-bit data channels. Data can travel on any of two rings going clockwise and two rings going counterclockwise.

    The EIB carries data traveling from the PPE and L2 cache to the SPEs and back again. It also connects this data to the Memory Interface Controller (MIC) and the FexIO Front Side Bus (FlexIO FSB). Through the MIC and FlexIO FSB, the EIB moves data from all those inner processors to parts of the computer outside the CPU, including system memory.

    It’s notable that the MIC is located on-chip. The AMD64 also offers this, but the AMD64’s reasonable memory bandwidth of 6.4 GB/s doesn’t even compare to Cell’s. The MIC on a Cell chip is designed to run at 25.6 GB/s (dual 12.8 GB/s channels). That certainly shouldn't be a bottleneck.

    The FlexIO FSB, like any front side bus, is what the processor uses to talk to the other parts of the computer. The FlexIO, however, will have two types of data that it transmits. One, called non-coherent (anyone’s guess as to why it’s not incoherent), is used for talking to sound cards, video cards, etc. This is what FSBs have been traditionally for. The other kind will be coherent data traffic, used to send and recieve data from other Cell processors. Since the Cell and its software are designed to operate by dividing packets and processing cooperatively, linking up a bunch of Cell processors will make a larger and more efficient cooperative processing system. It’s expected that Cell will be extremely powerful for stream processing.

    To be able to allow these speedy processors to communicate with each other and the rest of the machine, the FlexIO FSB has be pretty fast. Between both sets of data traffic, the bandwidth is 76.8 GB/s. To compare to our x86 counterpart, the AMD64 can only handle up to 8 GB/s bandwidth.

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       · thanks for writing this. Clear and concise, you help take the mystery out of the...
       · Thank you very much. I was trying to make Cell a bit easier to understand than some...
       · [quote]My only question is why aren't Apple moving to Cell technology instead of...
       · >>My personal feeling is Intel's long time strategy of comping ad dollars. When was...
       · one thing this article mentions that shows up in a lot of the cell hype is the idea...
       · That's a good comment. The reason I wrote vaguely (and everyone else has) is because...
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       · Intel video hardware is utter rubbish and is not something you want on a high end...
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       · Hi, it's nice to hear Mac users' opinions on this. A lot of people who speculate say...
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