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COMPUTER PROCESSORS

Cell Inside, the Future of Processor Architecture
By: Developer Shed
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    2005-06-29

    Table of Contents:
  • Cell Inside, the Future of Processor Architecture
  • Cell Architecture
  • PowerPC Processing Element (PPE)
  • Synergistic Processing Element (SPE)
  • Element Interface Bus (EIB)
  • The Future of Cell and x86
  • It's the Software

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    Cell Inside, the Future of Processor Architecture - PowerPC Processing Element (PPE)


    (Page 3 of 7 )

    The PPE, as the name suggests, consists of one of IBM’s robust PowerPC chips. The purpose of the PPE is to receive the information to be processed. When data enters the PPE, this element then cuts it up into bite size pieces and schedules it to be processed on one or more of the processors it controls, the Synergistic Processing Elements (SPEs). Then it distributes it to those SPE sub-processors and synchronizes everything.

    Though IBM has some very competant PowerPC chips already, this is not a clone of one that we’ve seen before. We only know a little about it. It is specially designed, featuring dual-threading, 64-bits, and Reduced Instruction Set Computing (RISC). So, much like the most high-end processors from AMD, it operates at 64-bits instead of the ordinary 32-bits. And much like the high-end Intel chips that are Hyperthreaded, the single core can process two threads of data simultaneously.

    Reduced Instruction Set Computing (RISC), for those not in the know, comes from a certain philosophy about computing, and neither Intel nor AMD can provide it on PCs due to compatibility issues. Normal processors accept a lot of instructions on how data is to be processed. RISC aims to reduce the instructions that processors use, thereby speeding up the hardware considerably. It also makes the hardware cheaper to produce since most of the control lies within the software. Unfortunately, this forces software developers to work harder.

    Like modern processors, the PPE has a cache to hold tasks to be processed on fast localized memory, an L1 of 32 KB and an L2 of 512 KB. Current AMD64 chips have this beaten already, with an L1 of 128 KB and L2 of up to 1 MB. The AMD64 definitely has a larger on-processor storage, but let’s not jump to conclusions yet. The AMD64 cache holds data for the one processor to crunch. The Cell’s PPE cache is more of a temporary holding area, where the PPE parcels the data and sends it off to a Synergistic Processing Element (SPE).

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       · thanks for writing this. Clear and concise, you help take the mystery out of the...
       · Thank you very much. I was trying to make Cell a bit easier to understand than some...
       · [quote]My only question is why aren't Apple moving to Cell technology instead of...
       · >>My personal feeling is Intel's long time strategy of comping ad dollars. When was...
       · one thing this article mentions that shows up in a lot of the cell hype is the idea...
       · That's a good comment. The reason I wrote vaguely (and everyone else has) is because...
       · I have no reason why apple decided to not adopt cell and instead adopt Intel the...
       · Intel video hardware is utter rubbish and is not something you want on a high end...
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       · Hi, it's nice to hear Mac users' opinions on this. A lot of people who speculate say...
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       · [quote]As to why they didn`t use cell, well this has been answered by you all...
     

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