AMD Sempron 3100+ Review - Commonalities
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The whole Sempron line has very little in common with the previous Durons anyway. With the lower end one's sporting the SocketA architecture, the previous AMD architecture of choice, Semprons are essentially remarked AthlonXP's built with the TbredB core. The one we are looking at today, however, is the lone ranger from the line sitting instead on socket754. Unlike with the previous naming scheme, the new Semprons are rated according to the equivalent Celeron. That's why some people are wondering why they can have a Sempron 3100+ which retails for less than an Athlon64 2800+, or why Semprons on socketA are slower than the previous ratings of TbredB's of identical speed.
When the first Newcastles came out, the drop going from 1024 to 512kb hardly caused a deficit, and only in certain applications at that. Whether the removal of cache is going to castrate this design the same way taking cache away from Intel’s Netburst design does is something we’ll answer today. However, in my experience, AMD's numbering system gets a little weak at the knees when the company’s marketing folks start adding models based on a cache increase alone.
So we've covered the fat AMD has trimmed (or at least disabled) from this CPU in terms of transistor count. What this then leaves us is a much leaner x86-32 processor. While a 1MB L2 cache Clawhammer is a pig for die space and transistor count on the 130nm process, Paris is much less so. This financially enables AMD to produce these cores in volume without putting an undue burden on the company’s shoulders. With the move to 90nm, this won't be as much of an issue, but that won't happen across the lineup until late 2005.
In the meantime, left over from its big brothers is the integrated memory controller. Now this is a positive use of the available transistor budget. Instead of the latency associated with shoving the data from memory over a front side bus from an off die controller, everything is handled on-chip. And with the design of the K8 not needing insane amounts of bandwidth, the single channel controller isn't a bottleneck like it is on the Intel side of things. Additionally, all the functional units are there and intact.
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