AMD AthlonXP 2500+ 333FSB Barton CPU
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With the release of the Barton series of CPU's, a new debate has taken the forums by storm. Does the increase in L2 cache from 256K to 512K, bringing the total on die cache to 640K up from 384K, really warrant another upgrade to your system? Today we are going to look at how the 2500+ Barton performs, and throw in the 2100+ T-bred AIUHB to see what improvements, if any, to expect.
When the rumor mill started on the Barton, we were supposed to get a 200MHz/400MHz FSB with it, and we were let down. The default Front Side bus of the current Barton's is 166MHz/333MHz FSB. Recently we have seen a few motherboard manufacturers release updated revisions to the nForce2 chipset (ABIT & ASUS) that will handle the 400MHz FSB by default, so hopefully the matching CPU from AMD isn't too far behind. On to the specs of the Barton.
- QuantiSpeed™ architecture for enhanced performance
- Nine-issue superpipelined, superscalar x86 processor microarchitecture designed for high performance
- Multiple parallel x86 instruction decoders
- Three out-of-order, superscalar, fully pipelined floating point execution units, which execute x87 (floating point), MMX™ and 3DNow!™ instructions
- Three out-of-order, superscalar, pipelined integer units
- Three out-of-order, superscalar, pipelined address calculation units
- 72-entry instruction control unit
- Advanced hardware data prefetch
- Exclusive and speculative Translation Look-aside Buffers
- Advanced dynamic branch prediction
- High-performance, full-speed on-chip cache (640K total)
- 3DNow!™ Professional technology (with 51 new instructions)
- 21 original 3DNow!™ instructions—the first technology enabling superscalar SIMD
- 19 additional instructions to enable improved integer math calculations for speech or video encoding and improved data movement for Internet plug-ins and other streaming applications
- 5 DSP instructions to improve soft modem, soft ADSL, Dolby Digital surround sound, and MP3 applications
- 52 SSE instructions with SIMD integer and floating point additions offer excellent compatibility with Intel’s SSE technology
The only noticeable change to the Barton core is the addition of the extra 256K L2 cache from the previous Thoroughbred core. Below we can see the progression from the Palomino core (XP1600 AGOIA), to the Thoroughbred core (XP2100 AIUHB), and finally the Barton Core (XP2500 AQUCA).
The Palomino was on the 0.15 micron process and while it ran the hottest of the cores, was a decent overclocker if you could find the 'magic' stepping. The move to the Thoroughbred core introduced the 0.13 micron process for AMD, and while the "A" version of the Thoroughbreds weren't the best overclockers, AMD refined the process, and added an extra layer to the core, and with the "B" version we started seeing better overclocking yields. AMD then graced us with the long awaited 333 MHz FSB that many enthusiasts were already running by overclocking their CPU's. With the 0.13 micron core process refined, and the 333 MHz FSB in place, AMD added the extra 256K of L2 cache, and the Barton was born. Intel users have long had the benefits of 512K L2 cache, but now Intel is pulling way ahead by ramping up the FSB on the P4's now at 533 MHz FSB, and very soon to 800 MHz FSB with the Canterwood. Hopefully AMD has some tricks up their sleeves to answer Intel's Canterwood, or I predict many diehard AMD fanatics looking for extreme performance will be jumping the fence to the Canterwood party. I know I am heavily contemplating it. I could bore you with endless technical crap, but if you're anything like me, you'd flip right past it, and want to see some benchmarks...So away we go...
Next: Testing and Benchmarks >>
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